Apparatus with Electronic Circuitry Having Reduced Leakage Current and Associated Methods

ABSTRACT

An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

TECHNICAL FIELD

The disclosure relates generally to electronic circuitry with improvedpower consumption and, more particularly, to integrated circuit (IC)apparatus with reduced power consumption, and associated methods.

BACKGROUND

Modern ICs have helped to integrate electronic circuitry to decreasesize and cost. As a consequence, modern ICs can form complex circuitryand systems. For example, virtually all of the functionality of a systemmay be realized using one or a handful of ICs. Such circuitry andsystems may receive and operate on both analog and digital signals, andmay provide analog and digital signals.

The result has been a growing trend to produce circuitry and systemswith increased numbers of transistors and similar devices. The increasednumber of devices has also coincided with increased power consumption ofelectronic circuits, such as ICs. Various mechanisms, such as deviceleakage, underlie the increased power consumption. Technologies such ascomplementary metal oxide semiconductor (CMOS), which are used in avariety of IC devices, use devices such as transistors with leakagecurrents.

The description in this section and any corresponding figure(s) areincluded as background information materials. The materials in thissection should not be considered as an admission that such materialsconstitute prior art to the present patent application.

SUMMARY

A variety of apparatus and associated methods are contemplated accordingto exemplary embodiments. According to one exemplary embodiment, anapparatus includes an IC, which includes CMOS circuitry that includes apull-up network coupled to a supply voltage and at least one inputsignal. The IC further includes a first metal oxide semiconductor (MOS)transistor coupled to the pull-up network and to a first bias voltage toreduce a gate-induced drain leakage (GIDL) current of the CMOScircuitry.

According to another exemplary embodiment, an apparatus includes an IC,which includes CMOS circuitry that includes a pull-down network coupledto a ground potential and at least one input signal. The IC furtherincludes a first MOS transistor coupled to the pull-down network and toa first bias voltage to reduce a GIDL current of the CMOS circuitry.

According to another exemplary embodiment, a method of reducing a GIDLcurrent of at least one transistor in a CMOS circuit includes biasing aMOS transistor coupled to the at least one transistor by applying a biasvoltage to a gate of the MOS transistor so as to reduce a drain-bulkvoltage of the at least one transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The appended drawings illustrate only exemplary embodiments andtherefore should not be considered as limiting the scope of theapplication or the claims. Persons of ordinary skill in the art willappreciate that the disclosed concepts lend themselves to other equallyeffective embodiments. In the drawings, the same numeral designatorsused in more than one drawing denote the same, similar, or equivalentfunctionality, components, or blocks.

FIG. 1 illustrates a leakage mechanism in one state of a CMOS inverter.

FIG. 2 depicts a leakage mechanism in another state of a CMOS inverter.

FIG. 3 shows a plot of leakage current as a function of the drain-bulkvoltage of a transistor.

FIG. 4 depicts a circuit arrangement for an inverter with reducedleakage current according to an exemplary embodiment.

FIG. 5 illustrates one state of a circuit arrangement for an inverterwith reduced leakage current according to an exemplary embodiment.

FIG. 6 depicts another state of a circuit arrangement for an inverterwith reduced leakage current according to an exemplary embodiment.

FIG. 7 illustrates a plot of leakage current as a function of biasvoltage according to an exemplary embodiment.

FIG. 8 shows a circuit arrangement for an inverter with reduced leakagecurrent according to an exemplary embodiment.

FIG. 9 illustrates a circuit arrangement for a CMOS circuit with reducedleakage current according to an exemplary embodiment.

FIG. 10 depicts a circuit arrangement for a NAND gate with reducedleakage current according to an exemplary embodiment.

FIG. 11 shows a circuit arrangement for a NOR gate with reduced leakagecurrent according to an exemplary embodiment.

FIGS. 12-15 illustrate leakage mechanisms in various states of a CMOStransmission gate.

FIG. 16 depicts a transmission gate with reduced leakage currentaccording to an exemplary embodiment.

FIG. 17 shows a circuit arrangement for a level shifter according to anexemplary embodiment.

FIG. 18 illustrates a circuit arrangement for a level shifter accordingto another exemplary embodiment.

FIG. 19 depicts a circuit arrangement for reducing leakage currentaccording to an exemplary embodiment.

FIG. 20 shows a block diagram of an IC according to another exemplaryembodiment.

DETAILED DESCRIPTION

The disclosed concepts relate generally to improving the performance ofelectronic circuitry. More specifically, the disclosed concepts provideapparatus and methods for reducing the leakage and, thus, improving orreducing the power consumption of, electronic circuitry, such as ICs.Rather than modifying the semiconductor fabrication process, thetechniques according to the disclosure use circuit-based approaches toreducing the leakage current of CMOS circuitry, as described below indetail.

CMOS circuitry, such as an inverter, can have several leakagemechanisms. For example, considering an inverter 10, as shown in FIG. 1,the gates of transistor 13 and transistor 16 tend to leak current. Inother words, the oxide layer used to construct the gates of thetransistors is not a perfect insulator, which results in some leakagecurrent. Generally, reverse-biased PN junctions will also leak a certainamount of current and therefore increase the overall leakage current ofinverter 10.

Inverter 10 in FIG. 1 also exhibits other leakage mechanisms. Forinstance, gate-induced drain leakage (GIDL) current may constitute arelatively large or substantial part of the total leakage current forCMOS circuits such as inverter 10. More specifically, GIDL maycontribute a relatively large or substantial amount to the overallleakage of CMOS circuits employing lightly-doped drain (LDD) transistorsdesigned for operation with relatively high supply voltages (V_(DD)),say, greater than 3 volts.

Generally, the GIDL mechanism and the effects of LDD are known to, andunderstood by, persons of ordinary skill in the art. A brief summary isprovided below.

GIDL is a phenomenon where current flows between the bulk and the drainregions of a metal-oxide-semiconductor field effect transistor (MOSFET)because of the bulk-drain junction getting modulated by the gate-drainvoltage. The GIDL phenomenon is sometimes associated with higher thannormal operating voltages (for example, write voltages used to writedate to flash memory cells). The GIDL phenomenon, however, can alsohappen at regular or nominal operating voltages in CMOS circuits whereLDD transistors are used. LDD transistors are typically used to allow ortolerate higher voltages across the bulk-drain PN-junctions oftransistors. Leakage because of the GIDL phenomenon is independent oftemperature.

GIDL is typically a relatively strong function of the drain-bulk voltage(V_(DB)) when the MOSFET is in the off state (i.e., the gate-sourcevoltage, V_(GS), is 0 or below the threshold voltage, V_(T)). Thiscondition is common in CMOS circuits. Consequently, GIDL can constitutea relatively large or even dominant leakage mechanism at roomtemperature for CMOS circuits.

Referring again to FIG. 1, inverter 10 includes P-channel MOS (PMOS)transistor 13 and N-channel MOS (NMOS) transistor 16. Assuming thattransistor 13 and transistor 16 constitute LDD transistors, when theinput voltage has a logic 1 value, transistor 16 is on, and transistor13 is off. The drain of transistor 13 is at or nearly at groundpotential (VSS) (because transistor 16 is on, thus pulling the output(OUT) to the ground potential, or logic 0), and the drain of transistor13 is coupled to the supply voltage.

Consequently, the drain-bulk voltage (V_(DB)) of transistor 13 isrelatively large, which leads to leakage because of GIDL. Path 18 showsthe path through which the leakage current flows. Specifically, currentflows from the supply source through transistor 13, through transistor16, and finally to the ground node.

A similar phenomenon causes GIDL current when the input voltage has alogic 0 value. FIG. 2 shows this situation. Referring to FIG. 2,transistor 13 is on and, thus, conducting. Conversely, transistor 16 isoff, as its gate-source voltage is below its threshold voltage.

Even though it is in the off state, transistor 16 has a relatively largedrain-bulk voltage (V_(DB)). More specifically, the drain of transistor16 has a relatively large voltage, i.e., at or near the supply voltage,as transistor 13 is on and pulls up the output node towards the supplyvoltage. The bulk of transistor 16, however, is coupled to the groundpotential. As a result, transistor 16 has a relatively large drain-bulkvoltage (V_(DB)), which leads to leakage because of GIDL. Path 18 showsthe path through which the leakage current flows. Specifically, currentflows from the supply source through transistor 13, through transistor16, and finally to the ground node through the bulk or bulk region oftransistor 16.

As noted, GIDL current of a transistor is a function of the drain-bulkvoltage (V_(DB)) of the transistor. FIG. 3 shows a plot 20 of leakagecurrent in a CMOS transistor as a function of the drain-bulk voltage.Specifically, the horizontal axis shows increasing values of thedrain-bulk voltage, from about 3 volts to about 3.9 volts. The verticalaxis shows GIDL current with the transistor in the off state (e.g.,V_(GS) is zero or nearly zero), and the source-bulk voltage (V_(SB))also zero or nearly zero. The numbers on the vertical axis are relativeto a drain-bulk voltage of 3 volts.

As curve 23 of the GIDL current shows, decreasing the drain-bulk voltage(V_(DB)) results in a corresponding decrease in the GIDL current. Forexample, as curve 23 illustrates, decreasing the drain-bulk voltage evenby ˜500 mV can decrease GIDL substantially, say, by a factor of nearly10. This property may be used to improve the GIDL current of variousCMOS circuits, such as inverters, logic gates, level shifters,transmission gates, etc., as described below in detail.

Generally speaking, CMOS circuits according to exemplary embodimentsemploy techniques to reduce the drain-bulk voltage (V_(DB)) seen by orapplied to a leaking device, such as an LDD PMOS or NMOS transistor. Insome embodiments, an additional PMOS transistor is coupled to a pull-uptransistor (e.g., the pull-up PMOS transistor of a CMOS inverter). FIG.4 depicts a circuit arrangement 30 for an inverter with reduced leakagecurrent according to an exemplary embodiment.

Specifically, the inverter in FIG. 4 includes pull-up PMOS transistor 33and pull-down NMOS transistor 36. In addition, the inverter includesGIDL current reduction PMOS transistor 39, coupled between transistor 33and the output node (OUT) of the inverter. More specifically, the sourceof transistor 39 is coupled to the drain of transistor 33, whereas thedrain of transistor 39 is coupled to the output node of the inverter.

Transistor 39 acts to reduce the effective drain-bulk voltage (V_(DB))of transistor 33 (the drain-bulk voltage seen by transistor 33 when itis in the off state). To facilitate this operation, the bulk or body oftransistor 39 is coupled to the supply voltage (V_(DD)) and the gate oftransistor 39 is coupled to a bias voltage (V_(bias)). The bias voltageis selected so as to cause a voltage drop across transistor 39, thusreducing the effective drain-bulk voltage of transistor 33. Thereduction of the drain-bulk voltage of transistor 33 causes a reductionin the GIDL current attributable to transistor 33.

Note that, in some embodiments, rather than including transistor 39 inseries with transistor 33, a GIDL current reduction NMOS transistor maybe added in series with transistor 36. The gate of such a transistorwould be coupled to a bias source of appropriate value in order todecrease the drain-bulk voltage of transistor 36. The reduction in thedrain-bulk voltage of transistor 36 would cause a reduction in the GIDLcurrent attributable to transistor 36. Furthermore in some embodiments,both a GIDL current reduction PMOS transistor and a GIDL currentreduction NMOS transistor may be used, as described below, for example,in connection with FIG. 8.

One aspect of the disclosure relates to generation of the bias voltageused to reduce leakage current, such as V_(bias) shown in FIG. 4. FIG. 5illustrates one state of a circuit arrangement 40 for providing a biasvoltage to a CMOS logic circuit (an inverter, in the example shown).Circuit arrangement 40 includes an inverter 43 coupled in cascade withan inverter 46. Inverter 43 and inverter 46 receive supply voltage froma voltage source labeled “V_(BIAS).” Thus, for CMOS inverters, theoutput voltages of inverter 43 and inverter 46 varies in the range ofV_(SS) (typically ground potential) and the supply voltage, V_(BIAS).

FIG. 5 illustrates the situation where the input voltage has a logic 1value (IN=1). In this case, the output of inverter 43 has a logic 0value, which results in the output of inverter 46 having a logic 1 value(labeled “V_(BIAS)”). The output of inverter 46 provides the biasvoltage to GIDL current reduction PMOS transistor 39. Thus, for a logic1 input value, inverter 46 provides a bias voltage of V_(BIAS).

FIG. 6 shows the situation where the input voltage has a logic 0 value(IN=0). In this situation, the output of inverter 43 has a logic 1value, which results in the output of inverter 46 having a logic 0 value(labeled “0”). The output of inverter 46 provides the bias voltage toGIDL current reduction PMOS transistor 39. Thus, for a logic 0 inputvalue, inverter 46 provides a bias voltage of 0 volts (groundpotential).

As FIGS. 5-6 illustrate, using inverter 43 and inverter 46 provides amechanism for providing a bias voltage that varies in response to theinput signal to a CMOS logic circuit. In other words, the bias voltageprovided is adaptive, in that it adapts in response to the values of theinput voltage applied to the CMOS logic circuit. Note that a similararrangement may be applied to situations where a GIDL current reductionNMOS transistor is added in series with transistor 36 (described above),or in the case where both a GIDL current reduction PMOS transistor and aGIDL current reduction NMOS transistor are used (described above).

One aspect of the disclosure relates to providing one or more variable(or configurable or adjustable or programmable) bias voltages to one ormore CMOS logic circuits in order to reduce GIDL current. FIG. 7illustrates a plot 50 of leakage current as a function of bias voltageaccording to an exemplary embodiment. Plot 50 includes curve 53, whichshows results of simulation of GIDL current as a function of biasvoltage (labeled “V_(BIAS)”). More specifically, curve 53 provides theresults for a CMOS inverter with a supply voltage of 3.8 volts, and isnormalized to a regular CMOS inverter (i.e., with no GIDL currentreduction) when V_(BIAS) is swept between the ground potential (0 volts)and the supply voltage (V_(DD)).

As FIG. 7 illustrates, GIDL current is optimized when the bias voltagehas a value close to half of the supply voltage, i.e., V_(BIAS)≈½V_(DD).Thus, in some embodiments, a bias voltage is used with a value of halfthe supply voltage, or near half of the supply voltage (e.g.,substantially equal to half the supply voltage, for example, within 5%,10%, or 20% of the supply voltage, etc.). Note that such bias voltagesmay be applied to GIDL current reduction PMOS transistor(s) and/or GIDLcurrent reduction NMOS transistor(s), as desired.

For basic logic gates, such as an inverter, a simpler option is to usefixed bias voltages. For instance, in some embodiments, a bias voltageof 0 volts (ground potential) is used for GIDL current reduction PMOStransistor(s), and/or the supply voltage (VDD) is used as a bias voltageGIDL current reduction NMOS transistor(s). This scheme provides atradeoff between circuit complexity and performance, for instance,compared to bias voltages with arbitrary or variable values.

As noted above, in some embodiments, both GIDL current reduction PMOStransistor(s) and GIDL current reduction NMOS transistor(s) are used.FIG. 8 shows a circuit arrangement 60 for a CMOS inverter that uses thisconfiguration.

More specifically, the inverter in FIG. 8 includes pull-up PMOStransistor 33 and pull-down NMOS transistor 36. The inverter alsoincludes GIDL current reduction PMOS transistor 39, coupled betweentransistor 33 and the output node (OUT) of the inverter. Morespecifically, the source of transistor 39 is coupled to the drain oftransistor 33, whereas the drain of transistor 39 is coupled to theoutput node of the inverter.

Transistor 39 acts to reduce the effective drain-bulk voltage (V_(DB))of transistor 33 (the drain-bulk voltage seen by transistor 33 when itis in the off state). To facilitate this operation, the bulk or body oftransistor 39 is coupled to the supply voltage (V_(DD)) and the gate oftransistor 39 is coupled to a bias voltage which, in the embodimentshown, is ground potential. The bias voltage is selected so as to reducethe effective drain-bulk voltage of transistor 33. The reduction of thedrain-bulk voltage of transistor 33 causes a reduction in the GIDLcurrent attributable to transistor 33.

The inverter also includes GIDL current reduction NMOS transistor 63,coupled between transistor 36 and the output node (OUT) of the inverter.More specifically, the source of transistor 63 is coupled to the drainof transistor 36, whereas the drain of transistor 63 is coupled to theoutput node of the inverter.

Transistor 63 acts to reduce the effective drain-bulk voltage (V_(DB))of transistor 36 (the drain-bulk voltage seen by transistor 36 when itis in the off state). To facilitate this operation, the bulk or body oftransistor 63 is coupled to the ground potential and the gate oftransistor 63 is coupled to a bias voltage which, in the embodimentshown, is the supply voltage (V_(DD)). The bias voltage is selected soas to reduce the effective drain-bulk voltage of transistor 36. Thereduction of the drain-bulk voltage of transistor 36 causes a reductionin the GIDL current attributable to transistor 36.

Note that, as discussed above, circuit arrangement 60 uses fixed biasvoltages, i.e., ground potential coupled to the gate of transistor 39,and the supply voltage coupled to the gate of transistor 63. In otherembodiments, however, the bias voltage applied to transistor 39 and/orthe bias voltage applied to transistor 63 may be variable (orconfigurable or adjustable or programmable), as discussed above.

The use of GIDL current reduction PMOS transistor 39 and/or GIDL currentreduction NMOS transistor 63 may be applied generally to various CMOScircuits. FIG. 9 illustrates a circuit arrangement 70 for a CMOS circuitwith reduced leakage current according to an exemplary embodiment. Thebulk or body nodes of PMOS transistors and the bulk and body nodes ofNMOS transistors in circuit arrangement 70 are coupled to the supplyvoltage (V_(DD)) and ground potential (V_(SS)), respectively.

Circuit arrangement 70 includes pull-up network 73, which is coupled toreceive the supply voltage (V_(DD)) and one or more inputs (labeled“IN”) of the CMOS circuit. Note that not all transistors in pull-upnetwork 73 are necessarily coupled to the supply voltage or theinput(s). Pull-up network 73 typically includes one or more PMOStransistors.

Similar to the inverter shown in FIG. 8, GIDL current reduction PMOStransistor 39 in FIG. 9 is coupled between pull-up network 73 and theoutput node (labeled “OUT”) of the CMOS circuit. The bulk or body oftransistor 39 is coupled to the supply voltage (V_(DD)). The gate oftransistor 39 is coupled to a bias voltage V_(BIASP), which may be fixedor variable (or configurable or adjustable or programmable), asdescribed above.

Furthermore, the CMOS circuit in FIG. 9 includes a pull-down network,which is coupled to the ground potential and to one or more inputs(labeled “IN”) of the CMOS circuit. Note that not all transistors inpull-down network 76 are necessarily coupled to the ground potential orthe input(s).

Similar to the inverter shown in FIG. 8, GIDL current reduction NMOStransistor 63 in FIG. 9 is coupled between pull-down network 76 and theoutput node (labeled “OUT”) of the CMOS circuit. The bulk or body oftransistor 63 is coupled to the ground potential or V_(SS). The gate oftransistor 63 is coupled to a bias voltage V_(BIASN), which may be fixedor variable (or configurable or adjustable or programmable), asdescribed above.

Note that in some embodiments, the bias voltages V_(BIASP) and V_(BIASN)might be the same, for example, one half of the supply voltage, asdescribed above. In other embodiments, however, the bias voltagesV_(BIASP) and V_(BIASN) might different values.

The use of GIDL current reduction PMOS transistor 39 and GIDL currentreduction NMOS transistor 63 reduces the drain-bulk voltage (V_(DB))seen by or applied to the transistor(s) in pull-up network 73 and/orpull-down network 76, as described above. As a result, the GIDL currentin the CMOS circuit is reduced.

Note that, rather than using both GIDL current reduction PMOS transistor39 and GIDL current reduction NMOS transistor 63, in some embodimentsone or the other transistor is used to reduce GIDL current in the CMOScircuit. More specifically, in some embodiments, the CMOS circuitincludes pull-up network 73 coupled to GIDL current reduction PMOStransistor 39, and a pull-down network 76 (in other words, GIDL currentreduction NMOS transistor 63 is omitted). Conversely, in someembodiments, the CMOS circuit includes pull-down network 76 coupled toGIDL current reduction NMOS transistor 63, and a pull-up network 73 (inother words, GIDL current reduction PMOS transistor 39 is omitted).

Referring again to FIG. 9, as persons of ordinary skill in the art willunderstand, pull-up network 73 and pull-down network 76 include one ormore MOSFETs. More specifically, in exemplary embodiments, pull-upnetwork 73 includes one or more PMOS transistors. Conversely, pull-downnetwork 76 includes one or more NMOS transistors.

The configuration of the transistors in pull-up network 73 and pull-downnetwork 76 determines the overall logic function that the CMOS circuitperforms. For example, FIG. 10 depicts a circuit arrangement 90 for aNAND gate with reduced leakage current according to an exemplaryembodiment.

The pull-up network in the NAND gate includes transistor 93 coupled toreceive input IN2 and transistor 96 coupled to receive input IN1 of theNAND gate. GIDL current reduction PMOS transistor 39 is coupled betweentransistor 96 and the output node (labeled “OUT”) of the NAND gate. Thegate of transistor 39 is biased by the ground potential, although otherbias voltages may be used, as described above.

Conversely, the pull-down network in the NAND gate includes transistor105 coupled to receive input IN1 and transistor 108 coupled to receiveinput IN2 of the NAND gate. GIDL current reduction NMOS transistor 63 iscoupled between transistors 105 and 108 and the output node (labeled“OUT”) of the NAND gate. The gate of transistor 63 is biased by thesupply voltage (V_(DD)), although other bias voltages may be used, asdescribed above.

FIG. 11 shows a circuit arrangement 120 for a NOR gate with reducedleakage current according to an exemplary embodiment. The pull-upnetwork in the NOR gate includes transistor 126 coupled to receive inputIN1 and transistor 123 coupled to receive input IN2 of the NOR gate.GIDL current reduction PMOS transistor 39 is coupled between transistors123 and 126 and the output node (labeled “OUT”) of the NOR gate. Thegate of transistor 39 is biased by the ground potential, although otherbias voltages may be used, as described above.

Conversely, the pull-down network in the NOR gate includes transistor135 coupled to receive input IN1 and transistor 138 coupled to receiveinput IN1 of the NOR gate. GIDL current reduction NMOS transistor 63 iscoupled between transistor 135 and the output node (labeled “OUT”) ofthe NOR gate. The gate of transistor 63 is biased by the supply voltage(V_(DD)), although other bias voltages may be used, as described above.

One aspect of the disclosure relates to reducing GIDL current in CMOStransmission gates. FIGS. 12-15 illustrate leakage mechanisms in variousstates of a CMOS transmission gate 150. Transmission gate 150 includesNMOS transistor 153 and PMOS transistor 156, coupled to the input(labeled “IN”) and output (labeled “OUT”) nodes. In response to theenable signal (labeled “EN”) and the logical complement of the enablesignal (labeled “ENB”), transistor 153 either couple the input to theoutput (when transmission gate 150 is on) or isolate the input from theoutput (when transmission gate 150 is off).

Transmission gate 150 includes multiple paths where GIDL currents flowwhen EN=0 (i.e., ENB=1, and transmission gate 150 is off), depending onthe state of the input and output signals, i.e., “IN” and “OUT.” FIGS.12-15 show paths 18 through which the leakage current flows, dependingon the states of the input and output signals, as Table 1 belowindicates:

TABLE 1 FIG. EN ENB IN OUT 12 0 1 0 0 13 0 1 1 0 14 0 1 0 1 15 0 1 1 1

GIDL current reduction transistors may be used to reduced the leakagecurrent of CMOS transmission gates. FIG. 16 depicts a circuitarrangement 180 for a transmission gate with reduced leakage currentaccording to an exemplary embodiment. The transmission gate includestransistor 153, driven by the EN signal, and transistor 156, driven bythe ENB signal.

In addition, the transmission gates includes GIDL current reduction NMOStransistors 183 and 186. Transistor 183 is coupled between the input ofthe transmission gate and transistor 153. Conversely, transistor 186 iscoupled between the output of the transmission gate and transistor 153.The gates of transistors 183 and 186 are coupled to a bias voltage,V_(DD), in the example shown, although other bias voltage values may beused, as discussed above.

The transmission gate further includes GIDL current reduction PMOStransistors 189 and 192. Transistor 189 is coupled between the input ofthe transmission gate and transistor 156. Conversely, transistor 192 iscoupled between the output of the transmission gate and transistor 156.The gates of transistors 189 and 192 are coupled to a bias voltage, theground potential in the example shown, although other bias voltagevalues may be used, as discussed above.

The bulk or body regions of the NMOS transistors in the transmissiongate are coupled to the ground potential. The bulk or body regions ofthe PMOS transistors in the transmission gate are coupled to the supplyvoltage (V_(DD)).

One aspect of the disclosure relates reducing GIDL current in CMOS levelshifters. FIG. 17 shows a circuit arrangement 210 for a level shifteraccording to an exemplary embodiment. The level shifter constitutes alow-to-high level shifter, and includes GIDL current reductioncircuitry.

The level shifter includes inverter 231 coupled in cascade with inverter234. The cascade of the two inverters buffers the input voltage (labeled“IN”). The output of inverter 231 (labeled “INB”) drives the gate oftransistor 228. The output of inverter 234 (labeled “INX”) drives thegate of transistor 225.

Transistor 225 is cross-coupled with transistor 216. More specifically,the drain of transistor 225 is coupled to the gate of transistor 216.Similarly, transistor 228 is cross-coupled with transistor 213. Thus,the drain of transistor 228 is coupled to the gate of transistor 216.

Inverter 231 and inverter 234 use a power supply voltage V_(DDL).Transistors 213 and 216 are coupled to a supply voltage V_(DDH). Thesupply voltage V_(DDH) has a larger value than the supply voltageV_(DDL). Thus, the output of the level shifter, at the drain oftransistor 228, can drive follow-on circuitry (not shown) supplied bysupply voltage V_(DDH).

Note that the gates of transistors 225 and 228 are driven by inverters231 and 234, respectively, which are supplied power from V_(DDL), arelatively low supply voltage (compared to V_(DDH)). With respect totransistor 213 and transistor 216, the level shifter includes additionalcircuitry to reduce the GIDL current of transistors 213 and 216. Morespecifically, the level shifter includes GIDL current reduction PMOStransistor 39A, coupled between transistor 213 and transistor 225. Thesource of transistor 39A is coupled to the drain of transistor 213. Thedrain of transistor 39A is coupled to the drain of transistor 225.

The gate of transistor 39A is coupled to the ground potential. Theaddition of transistor 39A reduces the drain-bulk voltage (V_(DB)) seenby or applied to transistor 213 in its off state. As a result, the GIDLcurrent contribution from transistor 213 is reduced.

Similarly, the level shifter includes GIDL current reduction PMOStransistor 39B, coupled between transistor 216 and transistor 228. Thesource of transistor 39B is coupled to the drain of transistor 216. Thedrain of transistor 39B is coupled to the drain of transistor 228.

The gate of transistor 39B is coupled to the ground potential. Theaddition of transistor 39B reduces the drain-bulk voltage (V_(DB)) seenby or applied to transistor 216 in its off state. As a result, the GIDLcurrent contribution from transistor 216 is reduced.

The bulk or body regions of NMOS transistors 225 and 228 are coupled toground potential. The bulk or body regions of PMOS transistors 213, 216,39A, and 39B are coupled to the supply voltage V_(DDH).

FIG. 18 illustrates a circuit arrangement 220 for a level shifteraccording to another exemplary embodiment. The level shifter in FIG. 18is similar to and operates similarly to the level shifter in FIG. 17,with the exception of the bias voltages applied to transistors 39A and39B. The level shifter in FIG. 18, however, uses an intermediate voltage(V_(DDL)) available in the circuit in order to further reduce the GIDLcurrent.

More specifically, the gate of transistor 39A is coupled to the voltage“INX” (described above) i.e., the voltage “INX” serves as a bias voltagefor transistor 39A. Similarly, the gate of transistor 39B is coupled tothe voltage “INB” (described above) i.e., the voltage “INB” serves as abias voltage for transistor 39B.

When the input voltage (IN) has a logic 1 value, the output voltage alsohas a logic 1 value. Transistor 213 is in the off state in thisscenario. Given that the voltage “INX” has the same (or nearly same,accounting for non-ideal characteristics of a practical implementation)voltage as the supply voltage V_(DDL), the drain of transistor 213 ismaintained at a voltage level of V_(DDL) plus the threshold voltage oftransistor 39A, thus reducing the drain-bulk voltage (V_(DB)) oftransistor 213 and, hence, its GIDL current contribution.

A similar analysis applies to transistors 39B and 216. In this case, thegate of transistor 39B is biased by the voltage “INB” which, similar tothe voltage “INX,” has the same (or nearly same, accounting fornon-ideal characteristics of a practical implementation) voltage as thesupply voltage V_(DDL). Consequently, the drain-bulk voltage (V_(DB)) oftransistor 216 and, hence, its GIDL current contribution are reduced.

The circuitry and techniques described above can be used to reduce theGIDL current of various CMOS circuitry. Simulation has shown that theGIDL current reduction may range 2 to 15 times in exemplary embodiments,depending on supply voltage, the bias voltage(s) used, and the type oflogic gate.

One aspect of the disclosure relates to the generation of bias voltagesin response to variables such as supply voltage. FIG. 19 depicts acircuit arrangement 300 for reducing leakage current according to anexemplary embodiment.

Circuit arrangement 300 includes an IC 305, which receives a supplyvoltage V_(DD). The supply voltage V_(DD) is provided to bias voltagegenerator 310. As noted above, the magnitude of the GIDL current for agiven CMOS circuit depends in part on the supply voltage used. Inresponse to the level of the supply voltage V_(DD), generates a biasvoltage V_(BIASP) for GIDL current reduction PMOS transistor(s) (notshown) in the IC. Similarly, in response to the level of the supplyvoltage V_(DD), generates a bias voltage V_(BIASN) for GIDL currentreduction PMOS transistor(s) (not shown) in the IC. The bias voltagesV_(BIASP) and V_(BIASN) are used in CMOS circuitry (not shown) in the ICto reduce GIDL current, as described above.

Optionally, bias voltage generator 310 may respond to one or more inputsignals 315. More specifically, bias voltage generator 310 in someembodiments generates the bias voltages V_(BIASP) and V_(BIASN)depending on the level or type of input signal(s) 315. In someembodiments, one or more signals may be used to control the level ofbias voltage(s) that bias voltage generator 310 generates.

For example, one or more signals may be used to control whether biasvoltage generator 310 generates fixed or variable bias voltage(s). Asanother example, one or more signals may be used to control the level ofchange in the bias voltage(s) in response to a given amount of change inone or more variables, for instance, the amount of change in the supplyvoltage V_(DD). As another example, one or more control signals may beused to control whether one or another set of fixed bias voltages isused (for instance, V_(DD) and ground potential are used as V_(BIASP)and V_(BIASN), respective, or ½VDD is used for both V_(BIASP) andV_(BIASN)). As another example, one or more control signals may be usedto control whether one or both of bias voltages V_(BIASP) and V_(BIASN)is variable (e.g., one fixed bias voltage and one variable bias voltage,both fixed bias voltages, or both variable bias voltages).

Other variations in the configuration and control of bias voltagegenerator 310 are possible and contemplated, as persons of ordinaryskill in the art will understand. The choice of configuration andcontrol of bias voltage generator 310 in a given implementation dependson a variety of factors, as persons of ordinary skill in the art willunderstand. Such factors include design specifications, performancespecifications, the level of GIDL current reduction desired, circuitcomplexity, cost, IC or device area, available technology, such assemiconductor fabrication technology, target markets, target end-users,etc.

Note that in some embodiments, rather than providing two bias voltages,bias voltage generator 310 may generate one bias voltage. For example,in some embodiments, generator 310 may generate V_(BIASP) but notV_(BIASN). As another example, in some embodiments, generator 310 maygenerate V_(BIASN) but not V_(BIASP). The choice of the number of biasvoltages depends on whether GIDL current reduction PMOS transistor(s),GIDL current reduction NMOS transistor(s), or both are used in a CMOScircuit.

Bias voltage generator 310 may be implemented in a variety of ways. Insome embodiments, a control circuit may be used to control the operationof bias voltage generator 310. In some embodiments, an analog circuit(e.g., an amplifier or scaling circuit) may be used to implement thegeneration of bias voltage(s) in response to the level of the supplyvoltage V_(DD). Generally, either analog circuitry or mixed-signalcircuitry may be used to implement bias voltage generator 310, dependingon factors such as design specifications, performance specifications,the level of GIDL current reduction desired, circuit complexity, cost,IC or device area, available technology, such as semiconductorfabrication technology, target markets, target end-users, etc., aspersons of ordinary skill in the art will understand.

As noted, GIDL current reduction circuitry according to variousembodiments may be used in a variety of circuitry, such as ICs. FIG. 20shows a block diagram of an IC 550 according to another exemplaryembodiment. In the particular example shown, IC 550 includes orconstitutes a microcontroller unit (MCU), although other types ofcircuitry or IC may be used, as persons of ordinary skill in the artwill understand.

Referring to FIG. 20, IC 550, which constitutes or includes an MCU. IC550 includes a number of blocks (e.g., processor(s) 565, data converter605, I/O circuitry 585, etc.) that communicate with one another using alink 560. In exemplary embodiments, link 560 may constitute a couplingmechanism, such as a bus, a set of conductors or semiconductors forcommunicating information, such as data, commands, status information,and the like.

IC 550 may include link 560 coupled to one or more processors 565, clockcircuitry 575, and power management circuitry or PMU 580. In someembodiments, processor(s) 565 may include circuitry or blocks forproviding computing functions, such as central-processing units (CPUs),arithmetic-logic units (ALUs), and the like. In some embodiments, inaddition, or as an alternative, processor(s) 565 may include one or moreDSPs. The DSPs may provide a variety of signal processing functions,such as arithmetic functions, filtering, delay blocks, and the like, asdesired.

Clock circuitry 575 may generate one or more clock signals thatfacilitate or control the timing of operations of one or more blocks inIC 550. Clock circuitry 575 may also control the timing of operationsthat use link 560. In some embodiments, clock circuitry 575 may provideone or more clock signals via link 560 to other blocks in IC 550.

In some embodiments, PMU 580 may reduce an apparatus's (e.g., IC 550)clock speed, turn off the clock, reduce power, turn off power, or anycombination of the foregoing with respect to part of a circuit or allcomponents of a circuit. Further, PMU 580 may turn on a clock, increasea clock rate, turn on power, increase power, or any combination of theforegoing in response to a transition from an inactive state to anactive state (such as when processor(s) 565 make a transition from alow-power or idle or sleep state to a normal operating state).

Link 560 may couple to one or more circuits 600 through serial interface595. Through serial interface 595, one or more circuits coupled to link560 may communicate with circuits 600. Circuits 600 may communicateusing one or more serial protocols, e.g., SMBUS, I²C, SPI, and the like,as person of ordinary skill in the art will understand.

Link 560 may couple to one or more peripherals 590 through I/O circuitry585. Through I/O circuitry 585, one or more peripherals 590 may coupleto link 560 and may therefore communicate with other blocks coupled tolink 560, e.g., processor(s) 365, memory circuit 625, etc.

In exemplary embodiments, peripherals 590 may include a variety ofcircuitry, blocks, and the like. Examples include I/O devices (keypads,keyboards, speakers, display devices, storage devices, timers, etc.).Note that in some embodiments, some peripherals 590 may be external toIC 550. Examples include keypads, speakers, and the like.

In some embodiments, with respect to some peripherals, I/O circuitry 585may be bypassed. In such embodiments, some peripherals 590 may couple toand communicate with link 560 without using I/O circuitry 585. Note thatin some embodiments, such peripherals may be external to IC 550, asdescribed above.

Link 560 may couple to analog circuitry 620 via data converter 605. Dataconverter 405 may include one or more ADCs 605B and/or one or more DACs605A. The ADC(s) 615 receive analog signal(s) from analog circuitry 620,and convert the analog signal(s) to a digital format, which theycommunicate to one or more blocks coupled to link 560.

Analog circuitry 620 may include a wide variety of circuitry thatprovides and/or receives analog signals. Examples include sensors,transducers, and the like, as person of ordinary skill in the art willunderstand. In some embodiments, analog circuitry 620 may communicatewith circuitry external to IC 550 to form more complex systems,sub-systems, control blocks, and information processing blocks, asdesired.

Control circuitry 570 couples to link 560. Thus, control circuitry 570may communicate with and/or control the operation of various blockscoupled to link 560. In addition, control circuitry 570 may facilitatecommunication or cooperation between various blocks coupled to link 560.

In some embodiments, control circuitry 570 may initiate or respond to areset operation. The reset operation may cause a reset of one or moreblocks coupled to link 560, of IC 550, etc., as person of ordinary skillin the art will understand. For example, control circuitry 570 may causePMU 580 to reset to an initial state. In some embodiments, thefunctionality and/or circuitry (or part thereof) of bias voltagegenerator 310 may be included in control circuitry 570, as desired.

In exemplary embodiments, control circuitry 570 may include a variety oftypes and blocks of circuitry. In some embodiments, control circuitry570 may include logic circuitry, finite-state machines (FSMs), or othercircuitry to perform a variety of operations, such as the operationsdescribed above.

Communication circuitry 640 couples to link 560 and also to circuitry orblocks (not shown) external to IC 550. Through communication circuitry640, various blocks coupled to link 560 (or IC 550, generally) cancommunicate with the external circuitry or blocks (not shown) via one ormore communication protocols. Examples include USB, Ethernet, and thelike. In exemplary embodiments, other communication protocols may beused, depending on factors such as specifications for a givenapplication, as person of ordinary skill in the art will understand.

As noted, memory circuit 625 couples to link 560. Consequently, memorycircuit 625 may communicate with one or more blocks coupled to link 560,such as processor(s) 365, control circuitry 570, I/O circuitry 585, etc.Memory circuit 625 provides storage for various information or data inIC 550, such as operands, flags, data, instructions, and the like, aspersons of ordinary skill in the art will understand. Memory circuit 625may support various protocols, such as double data rate (DDR), DDR2,DDR3, and the like, as desired. In some embodiments, the memory readand/or write operations involve the use of one or more blocks in IC 550,such as processor(s) 565. A direct memory access (DMA) arrangement (notshown) allows increased performance of memory operations in somesituations. More specifically, the DMA (not shown) provides a mechanismfor performing memory read and write operations directly between thesource or destination of the data and memory circuit 625, rather thanthrough blocks such as processor(s) 565.

Memory circuit 625 may include a variety of memory circuits or blocks.In the embodiment shown, memory circuit 625 includes non-volatile (NV)memory 635. In addition, or instead, memory circuit 625 may includevolatile memory (not shown). NV memory 635 may be used for storinginformation related to performance or configuration of one or moreblocks in IC 550. For example, NV memory 635 may store configurationinformation related to the operation of bias voltage generator 310, suchas the degree of change in the level of bias voltage(s) in response tochange, for example, in the level of the supply voltage, as describedabove.

IC 550 also includes bias voltage generator 310. As discussed above,bias voltage generator 310 operates in response to the supply voltageV_(DD) and, optionally, to input signal(s) 315. Bias voltage generator310 generates bias voltage V_(BIASP) and/or V_(BIASN). The biasvoltage(s) may be used to bias GIDL current reduction PMOS transistor(s)and/or GIDL current reduction NMOS transistor(s) used to reduce GIDLcurrent, as described above. More specifically, the bias voltage(s) maybe used to reduce GIDL current in one or more of the blocks of circuitryshown in IC 550 (or other desired circuitry), as described above.

Various circuits and blocks described above and used in exemplaryembodiments may be implemented in a variety of ways and using a varietyof circuit elements or blocks. For example, part of bias generator 310,pull-up network 73, and pull-down network 76 may generally beimplemented using digital circuitry. The digital circuitry may includecircuit elements or blocks such as gates, digital multiplexers (MUXs),latches, flip-flops, registers, finite state machines (FSMs),processors, programmable logic (e.g., field programmable gate arrays(FPGAs) or other types of programmable logic), arithmetic-logic units(ALUs), standard cells, custom cells, etc., as desired, and as personsof ordinary skill in the art will understand. In addition, analogcircuitry or mixed-signal circuitry or both may be included, forinstance, power converters, discrete devices (transistors, capacitors,resistors, inductors, diodes, etc.), and the like, as desired. Theanalog circuitry may include bias circuits, decoupling circuits,coupling circuits, supply circuits, current mirrors, current and/orvoltage sources, filters, amplifiers, converters, signal processingcircuits (e.g., multipliers), detectors, transducers, discretecomponents (transistors, diodes, resistors, capacitors, inductors),analog MUXs and the like, as desired, and as persons of ordinary skillin the art will understand. The mixed-signal circuitry may includeanalog to digital converters (ADCs), digital to analog converters(DACs), etc.) in addition to analog circuitry and digital circuitry, asdescribed above, and as persons of ordinary skill in the art willunderstand. The choice of circuitry for a given implementation dependson a variety of factors, as persons of ordinary skill in the art willunderstand. Such factors include design specifications, performancespecifications, cost, IC or device area, available technology, such assemiconductor fabrication technology), target markets, target end-users,etc.

Various other circuits and blocks described above and used in exemplaryembodiments may be implemented in a variety of ways and using a varietyof circuit elements or blocks. For example, part of bias generator 310or other mixed-signal circuitry (e.g., in IC 550 in FIG. 20) maygenerally be implemented using analog circuitry. The analog circuitrymay include bias circuits, decoupling circuits, coupling circuits,supply circuits, current mirrors, current and/or voltage sources,filters, amplifiers, converters, signal processing circuits (e.g.,multipliers), sensors or detectors, transducers, discrete components(transistors, diodes, resistors, capacitors, inductors), analog MUXs,and the like, as desired, and as persons of ordinary skill in the artwill understand. In addition, digital circuitry or mixed-signalcircuitry or both may be included. The digital circuitry may includecircuit elements or blocks such as gates, digital multiplexers (MUXs),latches, flip-flops, registers, finite state machines (FSMs),processors, programmable logic (e.g., field programmable gate arrays(FPGAs) or other types of programmable logic), arithmetic-logic units(ALUs), standard cells, custom cells, etc., as desired, and as personsof ordinary skill in the art will understand. The mixed-signal circuitrymay include analog to digital converters (ADCs), digital to analogconverters (DACs), etc.) in addition to analog circuitry and digitalcircuitry, as described above, and as persons of ordinary skill in theart will understand. The choice of circuitry for a given implementationdepends on a variety of factors, as persons of ordinary skill in the artwill understand. Such factors include design specifications, performancespecifications, cost, IC or device area, available technology, such assemiconductor fabrication technology), target markets, target end-users,etc.

Referring to the figures, persons of ordinary skill in the art will notethat the various blocks shown might depict mainly the conceptualfunctions and signal flow. The actual circuit implementation might ormight not contain separately identifiable hardware for the variousfunctional blocks and might or might not use the particular circuitryshown. For example, one may combine the functionality of various blocksinto one circuit block, as desired. Furthermore, one may realize thefunctionality of a single block in several circuit blocks, as desired.The choice of circuit implementation depends on various factors, such asparticular design and performance specifications for a givenimplementation. Other modifications and alternative embodiments inaddition to the embodiments in the disclosure will be apparent topersons of ordinary skill in the art. Accordingly, the disclosureteaches those skilled in the art the manner of carrying out thedisclosed concepts according to exemplary embodiments, and is to beconstrued as illustrative only. Where applicable, the figures might ormight not be drawn to scale, as persons of ordinary skill in the artwill understand.

The particular forms and embodiments shown and described constitutemerely exemplary embodiments. Persons skilled in the art may makevarious changes in the shape, size and arrangement of parts withoutdeparting from the scope of the disclosure. For example, persons skilledin the art may substitute equivalent elements for the elementsillustrated and described. Moreover, persons skilled in the art may usecertain features of the disclosed concepts independently of the use ofother features, without departing from the scope of the disclosure.

1. An apparatus comprising: an integrated circuit (IC) comprising:complementary metal oxide semiconductor (CMOS) circuitry comprising apull-up network coupled to a supply voltage and at least one inputsignal; and a first metal oxide semiconductor (MOS) transistor coupledto the pull-up network and to a first bias voltage to reduce agate-induced drain leakage (GIDL) current of the CMOS circuitry.
 2. Theapparatus according to claim 1, wherein the IC further comprises: apull-down network coupled to a ground potential and to the at least oneinput signal; and a second MOS transistor coupled to the pull-downnetwork and to a second bias voltage to reduce the GIDL current of theCMOS circuitry.
 3. The apparatus according to claim 1, wherein the firstbias voltage is applied to a gate of the first MOS transistor to reducea drain-bulk voltage of at least one transistor in the pull-up network.4. The apparatus according to claim 2, wherein the second bias voltageis applied to a gate of the second MOS transistor to reduce a drain-bulkvoltage of at least one transistor in the pull-down network.
 5. Theapparatus according to claim 2, wherein at least one of the first andsecond bias voltages is variable.
 6. The apparatus according to claim 1,wherein the first bias voltage depends on a supply voltage of the CMOScircuitry.
 7. The apparatus according to claim 2, wherein the secondbias voltage depends on a supply voltage of the CMOS circuitry.
 8. Anapparatus comprising: an integrated circuit (IC) comprising:complementary metal oxide semiconductor (CMOS) circuitry comprising apull-down network coupled to a ground potential and at least one inputsignal; and a first metal oxide semiconductor (MOS) transistor coupledto the pull-down network and to first a bias voltage to reduce agate-induced drain leakage (GIDL) current of the CMOS circuitry.
 9. Theapparatus according to claim 8, wherein the IC further comprises: apull-up network coupled to a supply voltage and to the at least oneinput signal; and a second MOS transistor coupled to the pull-up networkand to a second bias voltage to reduce the GIDL current of the CMOScircuitry.
 10. The apparatus according to claim 8, wherein the firstbias voltage is applied to a gate of the first MOS transistor to reducea drain-bulk voltage of at least one transistor in the pull-downnetwork.
 11. The apparatus according to claim 9, wherein the second biasvoltage is applied to a gate of the second MOS transistor to reduce adrain-bulk voltage of at least one transistor in the pull-up network.12. The apparatus according to claim 9, wherein at least one of thefirst and second bias voltages is variable.
 13. The apparatus accordingto claim 8, wherein the first bias voltage depends on a supply voltageof the CMOS circuitry.
 14. The apparatus according to claim 9, whereinthe second bias voltage depends on a supply voltage of the CMOScircuitry.
 15. A method of reducing a gate-induced drain leakage (GIDL)current of at least one transistor in a complementary metal oxidesemiconductor (CMOS) circuit, the method comprising biasing a metaloxide semiconductor (MOS) transistor coupled to the at least onetransistor by applying a bias voltage to a gate of the MOS transistor soas to reduce a drain-bulk voltage of the at least one transistor. 16.The method according to claim 15, wherein the at least one transistor isincluded in a pull-up network of the CMOS circuit.
 17. The methodaccording to claim 15, wherein the at least one transistor is includedin a pull-down network of the CMOS circuit.
 18. The method according toclaim 15, wherein the bias voltage is fixed.
 19. The method according toclaim 15, wherein the bias voltage is variable.
 20. The method accordingto claim 19, wherein the bias voltage depends on a supply voltage of theCMOS circuit.